1. Field of the Invention
The present invention relates to manufacturing methods for memory devices based on phase change materials including chalcogenide materials, and methods for forming doped chalcogenide materials for use in such devices.
2. Description of Related Art
Phase change based memory materials, like chalcogenide based materials and similar materials, can be caused to change between an amorphous phase and a crystalline phase by application of electrical current at levels suitable for implementation in integrated circuits. The amorphous phase is characterized by higher electrical resistivity than the crystalline phase, which can be readily read to indicate data. These properties have generated interest in using programmable resistive material to form non-volatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline phase is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process and allowing at least a portion of the phase change material to stabilize in the amorphous phase.
Chalcogenides and other phase change materials can be combined with additives to modify conductivity, transition temperature, melting temperature, and other properties of the material. Combining phase change materials with additives is sometimes referred to as “doping with impurities” or adding “dopants.” The terms “additive,” “dopant” or “impurity” can be used interchangeably in connection with this specification. Representative additives used with chalcogenides include nitrogen, silicon, oxygen, silicon oxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, for example, U.S. Pat. No. 6,800,504 (metal doping), and U.S. Patent Application Publication No. U.S. 2005/0029502 (nitrogen doping). Research has progressed to provide memory devices that operate with low reset current by adjusting the doping concentration in phase change memory.
Co-pending U.S. patent application entitled PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES, application Ser. No. 12/729,837, filed 23 Mar. 2010, describes the use of additives in chalcogenides for many purposes, and is incorporated by reference as if fully set forth herein. Dielectric additives, particularly silicon oxides and silicon nitrides which have been widely proposed for use with GST based chalcogenides, are difficult to implement in a way that produces sufficient yield for manufacturing. For example, co-sputtering using silicon oxide target and a chalcogenide target, while adjusting the powers applied to the two targets can be used to create silicon oxide doped chalcogenides. For example, see Ryu, et al., “SiO2 Incorporation Effects in Ge2Sb2Te5 Films Prepared by Magnetron Sputtering for Phase Change Random Access Memory Devices,” Electrochemical and Solid-State Letters, 9 (8) G259-G261 (2006); Lee et al., “Separate domain formation in Ge2Sb2Te5—SiOx mixed layer,” Appl. Phys. Lett. 89, 163503 (2006); Czubatyj et al., “Current Reduction in Ovonic Memory Devices,” E*PCOS06 (2006); Noh et al., “Modification of Ge2Sb2Te5 by the Addition of SiOx for Improved Operation of Phase Change Random Access Memory,” Mater. Res. Soc. Symp. Proc. Vol. 888 (2006), all of which described use of co-sputtering. A U.S. Patent Application Publication by Liang et al. (US 2009/0078924, published 26 Mar. 2009) describes formation of silicon oxide doped chalcogenides using reactive co-sputtering with a single element silicon target and a GST target, while adding oxygen using oxygen gas in the sputter chamber, at paragraph [0024] on page 2.
In connection with nitride compound additives, prior art U.S. Pat. No. 6,501,648, entitled PHASE CHANGE MATERIALS AND ASSOCIATED MEMORY DEVICES, by Chen et al., describes prior art co-sputtering, compound sputtering, and single element target, reactive sputtering techniques at Column 5, lines 54-63.
However, particles are produced in the co-sputtering process and the compound target process for dielectric additives, which contaminate the surface of the wafer and reduce yield.
Although substantial benefits in yield can be achieved using additives, issues remain concerning the manufacture of doped chalcogenides in a reliable and cost effective manner.
It is therefore desirable to provide memory cells addressing the yield, endurance, and data retention issues discussed above.